Design and implementation of an 11-bit non-linear interpolation DAC

Abstract

In this paper, a novel design of an 11 bit high speed digital-to-analog converter (DAC) is introduced. The design is integrated in a direct digital frequency synthesizer (DDFS). The proposed design consists of three modules, a linear DAC, a non-inear DAC and a non-inear interpolation DAC. The interpolation is based on the non-inearity in the I/V characteristic of the current cells used. The layout of the proposed DAC is carried out for a 3.3 V, 0.35 µm CMOS technology. Pre and post layout simulations are performed using Mentor Graphic Tools. The proposed DAC is simulated at 1 GHz clock frequency. The output frequency equals to 1/1024 f_clk with spurious free dynamic range (SFDR) of −50dB.