In this paper, a VLC decoder IC based on the table-lookup technique is described. In this design, a barrel shifter is employed to shift a number of bits corresponding to the decoded codeword. This parallel approach lowers the hardware speed constraint and reduces the system buffer memory size as well. The barrel shifter in conjunction with a codeword table and a word-length table makes the one-step decoding possible. The table storage required by this approach is the type of associative memory which is most efficiently implemented in Programmable Logic Arrays (PLAs). A Content Addressable Memory (CAM) approach that facilitates programmability is also addressed. Design considerations for multiple code tables and tables containing escape codes are discussed for more general applications of the decoder IC. The important issue of decoder interface circuitry, often ignored by others, is also fully considered. Such circuitry can greatly reduce the system complexity. Finally, the implementation of a mask programmable VLC decoder IC is demonstrated using a silicon compiler. Based on our simulations, the output symbol rate for a VLC decoder with 64 entries is about 30 MHz. This speed is high enough for most real-time applications including CCIR 601 digital video (Y: 13.5 MHz, U and V: 6.75 MHz each).