Code and Data Structure Partitioning for Parallel and Flexible MPSoC Specification Using Designer-Controlled Recoding
- 20 May 2008
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 27 (6), 1078-1090
- https://doi.org/10.1109/tcad.2008.923244
Abstract
MultiProcessor systems-on-chip (MPSoCs) are increasingly being used to build efficient and cost-effective embedded systems that meet the necessary real-time requirements. However, programming heterogeneous MPSoCs is highly challenging. The existing automatic parallelizing techniques, although effective on homogeneous shared-memory architectures, are insufficient for MPSoCs, which are typically characterized by heterogeneous processing elements and memory architectures. The lack of effective automatic techniques for recoding and parallelization requires designers to manually partition the code and the data structures in the reference application to generate a parallel and flexible specification model. Such manual algorithm partitioning by the designer is time consuming and error prone. In this paper, we motivate the need for automation in system specification and present a novel designer-controlled approach to recode applications written in a C-based System-Level Description Language. We present six automated source code transformations that, under the control of the designer, automatically partition and reorganize code and data structures to create a parallel and flexible abstract specification model that can be mapped onto a heterogeneous MPSoC using a top-down system-level design flow. Our experimental results show significant productivity gains and quality improvements in the end design.Keywords
This publication has 12 references indexed in Scilit:
- An Interactive Model Re-Coder for Efficient SoC SpecificationPublished by Springer Science and Business Media LLC ,2007
- Designer-controlled generation of parallel and flexible heterogeneous MPSoC specificationProceedings of the 39th conference on Design automation - DAC '02, 2007
- Creating Explicit Communication in SoC Models Using Interactive Re-CodingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2007
- Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific applicationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- A cycle-accurate compilation algorithm for custom pipelined datapathsPublished by Association for Computing Machinery (ACM) ,2005
- Parallel programming models for a multi-processor SoC platform applied to high-speed traffic managementPublished by Association for Computing Machinery (ACM) ,2004
- Networks on chips: a new SoC paradigmComputer, 2002
- Symbolic analysis for parallelizing compilersACM Transactions on Programming Languages and Systems, 1996
- Detecting coarse-grain parallelism using an interprocedural parallelizing compilerPublished by Association for Computing Machinery (ACM) ,1995
- A loop transformation theory and an algorithm to maximize parallelismIEEE Transactions on Parallel and Distributed Systems, 1991