Limited bandwidth to affect processor design
- 1 January 1997
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Micro
- Vol. 17 (6), 55-62
- https://doi.org/10.1109/40.641597
Abstract
In this article, we discuss how the effects of long memory latencies and increased memory bandwidth requirements may affect the design of modern microprocessors and their memory systems. In particular, we examine the subtle trade-offs between memory latency and bandwidth. Through execution-driven simulation, we measure the fraction of time that several SPEC95 benchmarks spend computing, stalled for memory latency, and stalled for limited memory bandwidth. Our results show that as processors implement more aggressive latency tolerance techniques, limited memory bandwidth negatively impacts programs much more than do long memory latencies. Finally, we survey a range of strategies for mitigating bandwidth limitations and discuss the relative merits and disadvantages of each.Keywords
This publication has 9 references indexed in Scilit:
- Decoupled sectored caches: conciliating low tag implementation cost and low miss ratioPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Creating a wider bus using caching techniquesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Memory bandwidth limitations of future microprocessorsPublished by Association for Computing Machinery (ACM) ,1996
- A modified approach to data cache managementPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1995
- A limit study of local memory requirements using value reuse profilesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1995
- A model for estimating trace-sample miss ratiosPublished by Association for Computing Machinery (ACM) ,1991
- Dynamic base register cachingPublished by Association for Computing Machinery (ACM) ,1991
- Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computersIEEE Transactions on Computers, 1990
- A VLIW architecture for a trace scheduling compilerIEEE Transactions on Computers, 1988