Reliability Analysis of Systems with Concurrent Error Detection
- 1 September 1975
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-24 (9), 868-878
- https://doi.org/10.1109/t-c.1975.224332
Abstract
There is an increasing use of error detectors and correctors in computer subsystems, such as parity detectors in memory modules and residue checkers in arithmetic units. Their fault tolerant characteristics are studied through the model of detector redundant systems. Their reliabilities and availabilities are analyzed and compared with those which do not have any such error detectors. The design of fault isolating and reconfiguring networks used in the implementation of such systems are developed.This publication has 12 references indexed in Scilit:
- The Design of a Microprogrammed Self-Checking Processor of an Electronic Switching SystemIEEE Transactions on Computers, 1973
- Design of a Self-Checking Microprogram ControlIEEE Transactions on Computers, 1973
- A framework for hardware-software tradeoffs in the design of fault-tolerant computersPublished by Association for Computing Machinery (ACM) ,1972
- An adaptive error correction scheme for computer memory systemPublished by Association for Computing Machinery (ACM) ,1972
- Arithmetic Error Codes: Cost and Effectiveness Studies for Application in Digital System DesignIEEE Transactions on Computers, 1971
- Cyclic and multiresidue codes for arithmetic operationsIEEE Transactions on Information Theory, 1971
- Reliability modeling techniques for self-repairing computer systemsPublished by Association for Computing Machinery (ACM) ,1969
- Design principles for processor maintainability in real-time systemsPublished by Association for Computing Machinery (ACM) ,1969
- Design of fault-tolerant computersPublished by Association for Computing Machinery (ACM) ,1967
- Estimates of Error Rates for Codes on Burst-Noise ChannelsBell System Technical Journal, 1963