Scalable 10Gbps TCP/IP Stack Architecture for Reconfigurable Hardware
- 1 May 2015
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
TCP/IP is the predominant communication protocol in modern networks but also one of the most demanding. Consequently, TCP/IP offload is becoming increasingly popular with standard network interface cards. TCP/IP Offload Engines have also emerged for FPGAs, and are being offered by vendors such as Intilop, Fraunhofer HHI, PLDA and Dini Group. With the target application being high-frequency trading, these implementations focus on low latency and support a limited session count. However, many more applications beyond high-frequency trading can potentially be accelerated inside an FPGA once TCP with high session count is available inside the fabric. This way, a network-attached FPGA on ingress and egress to a CPU can accelerate functions such as encryption, compression, memcached and many others in addition to running the complete network stack. This paper introduces a novel architecture for a 10Gbps line-rate TCP/IP stack for FPGAs that can scale with the number of sessions and thereby addresses these new applications. We prototyped the design on a VC709 development board, demonstrating compatibility with existing network infrastructure, operating at full 10Gbps throughput full-duplex while supporting 10,000 sessions. Finally, the design has been described primarily using high-level synthesis, which accelerates development time and improves maintainability.Keywords
This publication has 15 references indexed in Scilit:
- Loopy An open-source TCP/IP rapid prototyping and validation frameworkPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2013
- A 10 GbE TCP/IP hardware stack as part of a protocol acceleration platformPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2013
- A Low-Latency Library in FPGA Hardware for High-Frequency Trading (HFT)Published by Institute of Electrical and Electronics Engineers (IEEE) ,2012
- 40Gbps multi-connection TCP/IP offload enginePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2011
- A Simple Ethernet Stack Implementation in VHDL to Enable FPGA Logic ReconfigurabilityPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2011
- A Gigabit UDP/IP network stack in FPGAPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2009
- Hardware-Based TCP Processor for Gigabit EthernetIEEE Transactions on Nuclear Science, 2008
- Design and implementation of the high speed TCP/IP Offload EnginePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2007
- Design and Implementation of TCP/IP Offload Engine System over Gigabit EthernetProceedings of 15th International Conference on Computer Communications and Networks, 2006
- Congestion control in IP/TCP internetworksACM SIGCOMM Computer Communication Review, 1984