Optimization of phase-locked loop circuits via geometric programming
- 3 February 2004
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
We describe the global optimization of phase- locked loop (PLL) circuits using geometric programming (GP). Equations for the jitter, frequency range, and power of the PLL are presented in GP form. An array of PLL circuits was automatically generated using this technique in a , CMOS process. Silicon measurements show good agreement with the model. The results include a PLL with a period jitter of RMS and an accumulated jitter of RMS, consuming .Keywords
This publication has 3 references indexed in Scilit:
- Jitter optimization based on phase-locked loop design parametersIEEE Journal of Solid-State Circuits, 2002
- Jitter in ring oscillatorsIEEE Journal of Solid-State Circuits, 1997
- A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clock generationIEEE Journal of Solid-State Circuits, 1996