FPGA-accelerated retinal vessel-tree extraction
- 1 August 2009
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 1946147X,p. 485-488
- https://doi.org/10.1109/fpl.2009.5272498
Abstract
This work introduces an FPGA implementation for vessel tree extraction on retinal images. The retinal vessel-tree can be used in disease diagnoses, e.g. diabetes, or in person authentication. In such cases, a portable device with a high performance may be a need. The FPGA implementation discussed here, although application-oriented, features a fully programmable SIMD architecture, allowing for an efficient realization of low-level image processing algorithms. It is mapped onto a Spartan 3, amounting to 90 processing elements. The on-chip memory utilized was 1.4 MB and stores 8 gray images of 144 times 160 px. The working frequency is 53 MHz, allowing for a 3 times 3 convolution in less than 110 mus.Keywords
This publication has 8 references indexed in Scilit:
- iVisual: An Intelligent Visual Sensor SoC With 2790 fps CMOS Image Sensor and 205 GOPS/W Vision ProcessorIEEE Journal of Solid-State Circuits, 2008
- Arteriolar-to-venular diameter ratio estimation: A pixel-parallel approachPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2008
- SIMD array on FPGA for B/W image processingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2008
- Fast retinal vessel tree extraction: A pixel parallel approachInternational Journal of Circuit Theory and Applications, 2008
- Pixel parallel vessel tree extraction for a personal authentication systemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2008
- How fast is an FPGA in image processing?Published by Institute of Electrical and Electronics Engineers (IEEE) ,2008
- Personal authentication using digital retinal imagesPattern Analysis and Applications, 2006
- General-purpose 128×128 SIMD processor array with integrated image sensorElectronics Letters, 2006