Measurement of low Schottky barrier heights applied to metallic source/drain metal–oxide–semiconductor field effect transistors

Abstract

This article investigates the extraction of low Schottky barrier heights in the perspective of integration of metal–oxide–semiconductor field effect transistors (MOSFET) with a metallic source/drain. A test structure composed of two back-to-back junctions is proposed to characterize materials with a low Schottky barrier. To complete the proposed measurement setup, particular attention is placed on a Schottky transport model that continuously combines thermionic emission, field emission, and barrier lowering due to image charge. In the case of platinum silicide (PtSi) contact, it is shown that Arrhenius plots can be accurately reproduced over a wide range of temperature and applied bias. A consolidation of the measurement strategy and of the associated transport model is also performed through measurements and simulations on a long channel p-type Schottky barrier silicon-on-insulator MOSFET with PtSi source/drain. A excellent agreement between simulated and experimental current-voltage characteristics is obtained for a zero-field barrier height of 0.14 eV consistent with the value (0.145 eV) that best fits the Arrhenius plot measured on test structures. The corresponding bias-dependent effective barrier height in the 0.11–0.12 eV range is therefore confirmed at the device level.