Novel CMOS multi-bit counter for speed-power optimization in multiplier design
- 23 August 2018
- journal article
- research article
- Published by Elsevier BV in AEU - International Journal of Electronics and Communications
- Vol. 95, 189-198
- https://doi.org/10.1016/j.aeue.2018.08.015
Abstract
No abstract availableKeywords
This publication has 30 references indexed in Scilit:
- Low-latency MAP demapper architecture for coded modulation with iterative decodingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2014
- A novel fast glitchless 7-3 counter with a new structurePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2014
- VLSI implementation of ternary gates using Tanner ToolPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2014
- Improved matrix multiplier design for high‐speed digital signal processing applicationsIET Circuits, Devices & Systems, 2014
- Performance evaluation of high speed compressors for high speed multipliersSerbian Journal of Electrical Engineering, 2011
- Transmission Gate based High Performance Low Power MultiplierJournal of Applied Sciences, 2010
- High speed multiplier design using Decomposition LogicSerbian Journal of Electrical Engineering, 2009
- Novel architectures for efficient (m, n) parallel countersPublished by Association for Computing Machinery (ACM) ,2007
- High-speed multiplier design using multi-input counter and compressor circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A new design technique for column compression multipliersInternational Conference on Acoustics, Speech, and Signal Processing (ICASSP), 1995