Sparse Matrix-Vector Multiplication Design on FPGAs
- 1 April 2007
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007)
- p. 349-352
- https://doi.org/10.1109/fccm.2007.56
Abstract
Creating a high throughput sparse matrix vector multiplication (SpMxV) implementation depends on a balanced system design. In this paper, we introduce the innovative SpMxV solver designed for FPGAs (SSF). Besides high computational throughput, system performance is optimized by reducing initialization time and overheads, minimizing and overlapping I/O operations, and increasing scalability. SSF accepts any matrix size and can be easily adapted to different data formats. SSF minimizes the control logic by taking advantage of the data flow via an innovative accumulation circuit which uses pipelined floating point adders. Compared to optimized software codes on a Pentium 4 microprocessor, our design achieves up to 20x speedup.Keywords
This publication has 5 references indexed in Scilit:
- Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- Sparse Matrix-Vector multiplication on FPGAsPublished by Association for Computing Machinery (ACM) ,2005
- OSKI: A library of automatically tuned sparse matrix kernelsJournal of Physics: Conference Series, 2005
- FPGAs vs. CPUsPublished by Association for Computing Machinery (ACM) ,2004
- On sparse matrix-vector multiplication with FPGA-based systemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003