FPGA implementation of programmable Hybrid PUF using Butterfly and Arbiter PUF concepts
Physical Unclonable Functions (PUF) are physical entities that generates output as a function of process variation for a given input. It is an emerging hardware security solution to safeguard Intellectual Property, authentication of devices and to ensure data integrity through fingerprint generation. Delay based PUFs forms one of the popular category among different kinds of PUFs wherein the interconnect and gates delays due to uncontrollable manufacturing deviations are exploited to generate secret keys. However some of the designs such as arbiter and butterfly PUFs are seldom implemented in FPGA due to higher component of routing delay in comparison to random delay. This research work focus on the design of Hybrid PUF using the concepts of Butterfly and Arbiter PUF to reduce the skew delay factor in these PUFs. The proposed structure combines the benefits of both PUFs to increase the randomness and accuracy of the arbiter PUF. The architecture is designed to be programmable to work for any N-bit challenge as input. The PUF structures was simulated using Modelsim and Xilinx Vivado software version 19.2 were the tool used for implementing the design in spartan-7 FPGA.
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