Lightweight implementation of the POSIX threads API for an on-chip MIPS multiprocessor with VCI interconnect
- 1 March 2003
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in 2003 Design, Automation and Test in Europe Conference and Exhibition
Abstract
International audienceThis paper relates our experience in designing from scratch a multi-threaded kernel for a MIPS R3000 on-chip multiprocessor. We briefly present the target architecture build around a VCI compliant interconnect, and the CPU characteristics. Then we focus on the implementation of part of the POSIX 1003.1b and 1003.1c standards. We conclude this case study by simulation results obtained by cycle true simulation of an MJPEG video decoder application on the multiprocessor using several scheduler organizations and architectural parametersKeywords
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