Fabrication and Low Temperature Characterization of Ge (110) and (100) p-MOSFETs
- 16 May 2014
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 61 (6), 2215-2219
- https://doi.org/10.1109/ted.2014.2318083
Abstract
The Ge p-MOSFETs on (110) substrates using two-step implantation and NiGe contacts have been demonstrated. The record peak mobility of 528 cm 2 /V·s of the (110) Ge device is measured by the spilt C-V method and can be further enhanced by proper stress. Ge p-FETs on (110) substrates have lower mobility enhancement than (100) devices under compressive strain along the channel. The peak mobility decreases with decreasing temperature due to impurity scattering. The larger density of interface states causes the larger threshold voltage shift from the room temperature to 100 K as compared with Si MOSFETs.Keywords
Funding Information
- Ministry of Science and Technology, Taiwan (100-2221-E-002-181-MY3, 102-2120-M-002-001, 102-2218-E-002-003, 103-2911-I-009-302, 102-2622-E-002-014)
- Applied Materials
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