An 8-bit parallel DAC with segmented architecture
- 1 January 2017
- journal article
- Published by Pleiades Publishing Ltd in Journal of Communications Technology and Electronics
- Vol. 62 (1), 89-100
- https://doi.org/10.1134/S1064226917010053
Abstract
An 8-bit parallel DAC with a segmented architecture that employs a 4-bit binary and an unary segments is presented. A switched current source and a thermometric decoder are discussed. A test chip is fabricated using a 180-nm CMOS technology. Measured results show higher conversion rate and smaller chip area in comparison with other papers.Keywords
This publication has 9 references indexed in Scilit:
- A high resolution and high accuracy R-2R DAC based on ordered element matchingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2013
- A novel multi-step C-2C DAC architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2012
- Charge-redistribution DAC with double bit processing in single capacitorElectronics Letters, 2011
- Nonlinear R-2R Transistor-Only DACIEEE Transactions on Circuits and Systems I: Regular Papers, 2010
- Low-Cost 14-Bit Current-Steering DAC With a Randomized Thermometer-Coding MethodIEEE Transactions on Circuits and Systems II: Express Briefs, 2009
- An Improved Switch Compensation Technique for Inverted R-2R Ladder DACsIEEE Transactions on Circuits and Systems I: Regular Papers, 2008
- An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2008
- A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converterIEEE Journal of Solid-State Circuits, 2001
- A 10-b, 500-MSample/s CMOS DAC in 0.6 mm/sup 2/IEEE Journal of Solid-State Circuits, 1998