Design and implementation of a 16 by 16 low-power two's complement multiplier

Abstract

This paper describes the design and implementation of a high-speed low-power 16 by 16 two's complement parallel multiplier. The multiplier uses optimized radix-4 Booth encoders to generate the partial products, and an array of strategically placed (3,2), (5,3), and (7,4) counters to reduce the partial products to sum and carry vectors. The more significant bits of the product are computed from left to right using a modified Ercegovac-Lang converter. An implementation of the multiplier in 0.25- /spl mu/m static CMOS technology has an area of 0.126 mm/sup 2/, a measured delay of 4.39 ns, and a average power dissipation of 0.110 mW/MHz at 2.5 Volts and 100/spl deg/C.