Integrated power clock generators for low energy logic
- 19 November 2002
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 1, 61-67 vol.1
- https://doi.org/10.1109/pesc.1995.474793
Abstract
Low-energy (adiabatic) logic families have been proposed to reduce energy consumption of VLSI logic devices. Instead of the conventional DC power supply, these logic families require AC power supplies (power clocks) that allow energy recovery and also serve as timing clocks for the logic. In this paper, high-frequency resonant DC/AC inverters are proposed as power clock generators where all power switches and control circuitry are integrated on the same chip with low-energy logic. This results in better system efficiency and simpler power distribution. Closed-form results are derived to facilitate efficiency-optimized design of the proposed power clock generators. To illustrate system integration and energy savings, the optimized power clock is used to supply a novel clocked CMOS adiabatic logic (CAL).<>Keywords
This publication has 8 references indexed in Scilit:
- Adiabatic Computing with the 2n-2n2d Logic FamilyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Adiabatic Switching, Low Energy Computing, And The Physics Of Storing And Erasing InformationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Design of the zero-voltage-switching quasi-square-wave resonant switchPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Recovered energy logic-A highly efficient alternative to today's logic circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A review of adiabatic computingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Adiabatic dynamic logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A MOS gate drive with resonant transitionsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- PULSED LOW POWER CMOSInternational Journal of High Speed Electronics and Systems, 1994