A 3.3 V 16 Mb flash memory with advanced write automation

Abstract

The design of this flash memory is governed by the following considerations. Use of flash memory to store both data and code requires fast write with interruptible erase. Portable systems operate at 3.3 V to optimize battery life, while the desktop remains primarily a 5 V platform. This 16 Mb flash memory on a 0.6 /spl mu/m CMOS process operates with either 3.3 or 5 V supply. In the 3.3 V mode, a word line boost circuit is enabled, the input buffer trip points are modified, and the read path circuits are reconfigured for optimum performance. This memory uses the host computer 12 V supply to minimize flash media cost and maximize flash media performance. The device contains an advanced user interface that allows the host to queue up to three commands for execution by the write state machine, designed to allow erase to be interrupted so a program operation can be executed. Two 256B page buffers improve write performance and reduce host overhead. Wafer yields are improved by including redundant row pairs and columns.> Author(s) Baker, A. Intel Corp., Folsom, CA, USA Alexis, R. ; Bell, S. ; Dalvi, V. ; Durante, R. ; Baer, E. ; Fandrich, M. ; Jungroth, O. ; Kreifels, J. ; Landgraf, M. ; Lee, K. ; Pon, H. ; Rashid, M. ; Rozman, R. ; Tsang, J. ; Underwood, K. ; Yarlagadda, C.