All-digital PLL and GSM/edge transmitter in 90nm CMOS
- 30 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A 1.2V 42mA all-digital PLL and polar transmitter for a single-chip GSM/EDGE transceiver is implemented in 90nm CMOS. It transmits GMSK with 0.5/spl deg/ rms phase error and achieves -165dBc/Hz phase noise at 20MHz offset, with 10 /spl mu/s settling time. A digitally controlled 6dBm class-E PA modulates the amplitude and meets the EDGE spectral mask with 3.5% EVM.Keywords
This publication has 3 references indexed in Scilit:
- All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOSIEEE Journal of Solid-State Circuits, 2004
- All-digital phase-domain TX frequency synthesizer for Bluetooth radios in 0.13μm CMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- A first multigigahertz digitally controlled oscillator for wireless applicationsIEEE Transactions on Microwave Theory and Techniques, 2003