30 nm ultra-thin-body SOI MOSFET with selectively deposited Ge raised S/D

8 November 2002

conference paper
conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 23-24
https://doi.org/10.1109/drc.2000.877072

Abstract

MOSFETs with selectively deposited Ge raised source/drain (S/D) implemented in 8 nm ultra-thin-body (UTB) SOI are demonstrated. The Ge is selectively deposited by LPCVD and annealed at a low temperature using RTA (650/spl deg/C, 20 s). Devices with gate lengths down to 30 nm are obtained with 8 nm UTB and show excellent short-channel behavior.

This publication has 2 references indexed in Scilit:

Electrical properties of heavily doped polycrystalline silicon-germanium films
IEEE Transactions on Electron Devices, 1994
SOI (Silicon-On-Insulator) for High Speed Ultra Large Scale Integration
Japanese Journal of Applied Physics, 1994

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