Design considerations of a fast 0-Ω gate-drive circuit for 1.2 kV SiC JFET devices in phase-leg configuration
- 1 September 2009
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 23293721,p. 2293-2300
- https://doi.org/10.1109/ecce.2009.5316075
Abstract
This paper presents detailed design considerations of an ultra fast gate-drive circuit for 1.2 kV SiC JFET devices in phase-leg configuration using 0-Omega gate resistance. The proposed gate-drive achieved turn-on and turn-off times in the range of 12 to 55 ns operating from a 600 V dc bus with an inductive load of 10 A, and junction temperatures varying from 25deg to 200degC. An in-depth experimental evaluation is presented as well fully characterizing the performance attained by the proposed gate-drive circuit.Keywords
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