A Re-design Technique for Datapath Modules in Error Tolerant Applications

Abstract

Scaling CMOS into nano-scale is decreasing yields. The concept of error tolerance has been proposed to reverse this trend by developing new test techniques for chips used in many applications, such as audio, video, graphics, games, and error-correcting codes for wireless communication. In such chips, manufacturing defects that induce errors with severities within specified thresholds (determined via analysis of applications) are deemed acceptable. In this paper, we develop an approach to re-design datapath modules to exploit acceptable errors to improve yield. Under the manufacturing yield model (Y_m = Y_para * Y_func), parametric yield (Y_para) improvement due to decrease in delay is more important than functional yield (Y_func) improvement due to decrease in area. So our re-designing technique mainly focuses on reducing delay of datapath modules to improve parametric yield. In particular, we propose multiple approaches and apply them to improve yield of a wide range of adder architectures by exploiting error tolerance in these applications. Experiment results show that even for small thresholds on error severity, we can obtain significant improvements in manufacturing yield.