The different leakage components in a germanium MOS technology are studied, with the main focus on highly-doped p+/n junctions designed for short-channel Ge pFET fabrication. Three main components of junction leakage are discerned, depending on the position (the active area, the perimeter of the isolation, under the spacer). Each of these components shows a different temperature sensitivity, indicative of the different dominant leakage mechanisms. Suggestions are given to keep each component as low as possible. Furthermore, junction leakage results in novel thin selectively grown Ge-in-STI substrates are reported. These thin substrates offer lower perimeter leakage at the expense of a slightly higher area leakage. In a commercial design, however, the advantage of the lower perimeter current is expected to outweigh the effect of area leakage.