High-Efficiency CMOS RF-to-DC Rectifier Based on Dynamic Threshold Reduction Technique for Wireless Charging Applications
Open Access
- 21 August 2018
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Access
- Vol. 6, 46826-46832
- https://doi.org/10.1109/access.2018.2866457
Abstract
This paper presents a high-efficiency CMOS rectifier based on an improved dynamic threshold reduction technique (DTR). The proposed DTR consists of a clamper circuit that biases the gates of pMOS diode switches through a capacitor and diode-connected pMOS transistor. The clamper is used to insert a negative dc level to the input RF signal; therefore, more negative RF signal can be obtained to bias the gates of the main rectifying pMOS devices during its conduction phase. This mechanism reduces the threshold voltage of the main pMOS transistors and increases their sensitivity to the RF input signal. The proposed rectifier is implemented in a 0.18-μm CMOS technology and tested. The measurement shows a peak power conversion efficiency of 86% and an output voltage of 0.52 V at an input power of -16.5 dBm and an input frequency of 402 MHz. The core area of chip excluding measurement pads is 0.024 mm 2 .Funding Information
- University of Tokyo
- Egyptian Ministry of Higher Education (MoHE), Cairo, Egypt
- Egypt–Japan University of Science and Technology (EJUST), Alexandria, Egypt
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