A 45nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL

1 January 2006

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 1-4
https://doi.org/10.1109/iedm.2006.346878

Abstract

We present the state-of-the-art 45nm high performance bulk logic platform technology which utilizes, for the first time in the industry, ultra high NA (1.07) immersion lithography to realize highly down-scaled chip size. Fully renovated MOSFET integration scheme which features reversed extension and SD diffusion formation is established to meet Vt roll-off requirement with excellent transistor performance of Ion=1100muA/mum for nFET and Ion=700muA/mum for pFET at Ioff=100nA/mum. Also, we achieved excellent BEOL reliability and manufacturability by implementing hybrid dual-damascene (DD) structure with porous low-k film (keff=2.7)

Keywords

LOGIC
CMOS TECHNOLOGY
LITHOGRAPHY
SURFACE-MOUNT TECHNOLOGY
RANDOM ACCESS MEMORY
MOSFET CIRCUITS
DSL
BORON
DEGRADATION
LARGE SCALE INTEGRATION

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