Dynamic Partial Reconfiguration in FPGAs
- 1 January 2009
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 2, 445-448
- https://doi.org/10.1109/iita.2009.334
Abstract
Dynamic partial reconfigurable FPGAs offer new design space with a variety of benefits: reduce the configuration time and save memory as the partial reconfiguration files (bitstreams) are smaller than full ones. This paper introduces a simple reconfigurable system and focuses on the advantages of the newest dynamic partial reconfiguration design flow.Keywords
This publication has 3 references indexed in Scilit:
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- Handel-C Implementation of Early-Access Partial-Reconfiguration for Software Defined RadioPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2008
- A Self-Reconfigurable Adaptive FIR Filter System on Partial Reconfiguration PlatformIEICE Transactions on Information and Systems, 2007