Hierarchical Hybrid Memory Management in OS for Tiered Memory Systems
- 29 March 2019
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Parallel and Distributed Systems
- Vol. 30 (10), 2223-2236
- https://doi.org/10.1109/tpds.2019.2908175
Abstract
The emerging hybrid DRAM-NVM architecture is challenging the existing memory management mechanism at the level of the architecture and operating system. In this paper, we introduce Memos, a memory management framework which can hierarchically schedule memory resources over the entire memory hierarchy including cache, channels, and main memory comprising DRAM and NVM simultaneously. Powered by our newly designed kernel-level monitoring module that samples the memory patterns by combining TLB monitoring with page walks, and page migration engine, Memos can dynamically optimize the data placement in the memory hierarchy in response to the memory access pattern, current resource utilization, and memory medium features. Our experimental results show that Memos can achieve high memory utilization, improving system throughput by around 20.0 percent; reduce the memory energy consumption by up to 82.5 percent; and improve the NVM lifetime by up to 34X.Keywords
Funding Information
- National Key Research and Development Plan of China (2017YFB1001602)
- NSF (61502452)
This publication has 48 references indexed in Scilit:
- Profiling a warehouse-scale computerPublished by Association for Computing Machinery (ACM) ,2015
- Let's Talk About Storage & Recovery Methods for Non-Volatile Memory Database SystemsPublished by Association for Computing Machinery (ACM) ,2015
- WiseThrottling: a new asynchronous task scheduler for mitigating I/O bottleneck in large-scale datacenter serversThe Journal of Supercomputing, 2015
- Main Memory Scaling: Challenges and Solution DirectionsPublished by Springer Science and Business Media LLC ,2015
- Dynamic Data Migration in Hybrid Main Memories for In-Memory Big Data StorageETRI Journal, 2014
- BadgerTrapACM SIGARCH Computer Architecture News, 2014
- BPM/BPM+ACM Transactions on Architecture and Code Optimization, 2014
- Dynamic I/O-Aware Scheduling for Batch-Mode Applications on Chip Multiprocessor Systems of Cluster PlatformsJournal of Computer Science and Technology, 2014
- CLOCK-DWF: A Write-History-Aware Page Replacement Algorithm for Hybrid PCM and DRAM Memory ArchitecturesInternational Conference on Acoustics, Speech, and Signal Processing (ICASSP), 2013
- Extending Human Capabilities through Information Technology Applications and InfrastructuresInformation Technology for Development, 2010