Results from the best reported PMOS transistor at a 37 nm gate length (Lg) built on a process with a recessed SiGe epitaxial layer are discussed. The process details include successful integration of SiGe at the drain extension (DE) location. A highly compressive SiGe layer, in close proximity to the channel, results in large hole mobility improvements. HRTEM based lattice parameter extractions confirm the compressive strain in the channel. In situ doped B in SiGe can be activated to a higher degree than implanted B in bulk Si resulting in further improvements from the lower DE resistance. Both changes combine to give an unprecedented 35% PMOS performance improvement. Process and device simulations that predict the observed parametric behavior quantitatively isolate the improvements to be /spl sim/ 28% from stress and 7% from DE resistance improvement.