Low-voltage-driven top-gate ZnO thin-film transistors with polymer/high-k oxide double-layer dielectric

Abstract

The authors report on the fabrication of a low-voltage-driven top-gate ZnO thin-film transistor with a polymer/high-$k$ oxide double-layer dielectric. Hybrid double-layer dielectric $(k=\sim 9.8)$ was formed on patterned ZnO through sequential deposition processes: spin casting of $45\text{-}\mathrm{nm}$ -thin poly-4-vinylphenol and e-beam evaporation of $50\text{-}\mathrm{nm}$ -thick amorphous high-$k$ oxide ($\mathrm{Ce}{\mathrm{O}}_2–\mathrm{Si}{\mathrm{O}}_2$ mixture). Room-temperature-deposited ZnO channel exhibits much rougher surfaces compared to that of $100°\mathrm{C}$ deposited ZnO, so that enhanced device performances were achieved from a ZnO thin-film transistor (TFT) prepared with $100°\mathrm{C}$ deposited ZnO: $\sim 0.48{\mathrm{cm}}^2∕\mathrm{V}\mathrm{s}$ for field-effect mobility and $\sim 5\times {10}^3$ for on/off current ratio. Adopting our top-gate ZnO-TFT, a load-resistance inverter was set up and demonstrated decent static and dynamic operations at $3\mathrm{V}$ .