A full adder implementation using SET based linear threshold gates
- 25 June 2003
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
In this paper we investigate single electron tunneling (SET) devices from the logic design perspective, using the SET tunnel junction's ability to control the transport of in - dividual electrons. More in particular, we present the im- plementation of a Full Adder using SET threshold gates. First, we augment the threshold gates with an active buffer in order to overcome feedback effects which can appear in passive SET networks. Second, we derive the circuit pa- rameters for buffered SET threshold gates, and present the simulation results. Finally, we utilize the buffered thres h- old gates to build a Full Adder circuit, and verify the be- havior of the resulting circuit via simulation.Keywords
This publication has 7 references indexed in Scilit:
- A linear threshold gate implementation in single electron technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Single-electron logic and memory devicesInternational Journal of Electronics, 1999
- Single-electron devices and their applicationsProceedings of the IEEE, 1999
- SIMON-A simulator for single-electron tunnel devices and circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1997
- CMOS scaling into the nanometer regimeProceedings of the IEEE, 1997
- Possible performance of capacitively coupled single-electron transistors in digital circuitsJournal of Applied Physics, 1995
- Complementary digital logic based on the ‘‘Coulomb blockade’’Journal of Applied Physics, 1992