The design of a high speed ASIC unit for the hash function SHA-256 (384, 512)
- 20 July 2004
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 2 references indexed in Scilit:
- On the hardware implementations of the SHA-2 (256, 384, 512) hash functionsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- An efficient implementation of hash function processor for IPSECPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003