Cascaded voting process for flash ADC with interpolating scheme

Abstract

A 3-stage cascaded voting process is proposed for flash analogue-to-digital converters (ADCs) with an interpolation factor of 4 to eliminate the consecutive bubbles at the output nodes of the comparator array. Compared to the conventional 3-input voting process, the proposed process completely eliminates up to seven consecutive bubbles without hardware overhead, if the preamplifier output is assumed to have a single bubble at most. The proposed voting process is evaluated by 7-bit 1 GS/s CMOS flash ADCs with an interpolation factor of 4 which is designed by a 0.13 µm CMOS process with 1.2 V supply.