Estimation of power dissipation in CMOS combinational circuits

Abstract

It is shown that a simplified model of power dissipation relates maximizing dissipation to maximizing gate output activity, appropriately weighted to account for differing load capacitances. To find the input or input sequence that maximizes the weighted activity, algorithms are given for transforming the problem to a weighted max-satisfiability problem, and then exact and approximate algorithms for solving weighted max-satisfiability are given. That is, transformations are presented that convert a logic description into a multiple-output Boolean function of the input vector or vector sequence, where each output of the Boolean function is associated with a logic gate output transition. Algorithms for constructing the Boolean function for dynamic CMOS and static CMOS, which take into account dissipation due to glitching, are presented. Finally, efficient exact and approximate methods for solving the generated weighted max-satisfiability problem are presented.