Origins of threshold voltage shifts in room-temperature deposited and annealed a-In–Ga–Zn–O thin-film transistors

Abstract

Threshold voltage $\left(V_{\text{th}}\right)$ stability was examined under constant current stress for $a\text{-In}–\text{Ga}–\text{Zn}–\text{O}$ thin film transistors (TFTs) deposited at room temperature and annealed at $400°\text{C}$ in dry or wet ${\text{O}}_2$ atmospheres. All the TFTs exhibited positive $V_{\text{th}}$ shifts $\left(\Delta V_{\text{th}}\right)$ and the $\Delta V_{\text{th}}$ value was reduced by the thermal annealing to $<2\text{V}$ for 50 h. TFT simulations revealed that the $\Delta V_{\text{th}}$ for the annealed TFTs is explained by increase in deep charged defects. Large $\Delta V_{\text{th}}$ over 10 V and deterioration in subthreshold voltage swing were observed in the unannealed TFTs, which are attributed to the increase in shallow trap states.