Instruction-level power estimation for embedded VLIW cores
- 1 May 2000
- conference paper
- conference paper
- Published by Association for Computing Machinery (ACM) in Proceedings of the eighth international workshop on Hardware/software codesign - CODES '00
Abstract
This paper introduces a power estimation methodology operating at the instruction-level which is tightly related to the characteristics of the paralel system architecture, mainly in terms of one or more target processors, the memory sub-system, the system-level buses and the coprocessorsKeywords
This publication has 2 references indexed in Scilit:
- Power analysis and minimization techniques for embedded DSP softwareIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1997
- Power analysis of embedded software: a first step towards software power minimizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1994