Fast and processor efficient parallel matrix multiplication algorithms on a linear array with a reconfigurable pipelined bus system
- 1 January 1998
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Parallel and Distributed Systems
- Vol. 9 (8), 705-720
- https://doi.org/10.1109/71.706044
Abstract
No abstract availableKeywords
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