Exploiting memory allocations in clusterised many‐core architectures
Open Access
- 24 April 2019
- journal article
- research article
- Published by Institution of Engineering and Technology (IET) in IET Computers & Digital Techniques
- Vol. 13 (4), 302-311
- https://doi.org/10.1049/iet-cdt.2018.5136
Abstract
Power-efficient architectures have become the most important feature required for future embedded systems. Modern designs, like those released on mobile devices, reveal that clusterisation is the way to improve energy efficiency. However, such architectures are still limited by the memory subsystem (i.e. memory latency problems). This work investigates an alternative approach that exploits on-chip data locality to a large extent, through distributed shared memory systems that permit efficient reuse of on-chip mapped data in clusterised many-core architectures. First, this work reviews the current literature on memory allocations and explores the limitations of cluster-based many-core architectures. Then, several memory allocations are introduced and benchmarked scalability, performance and energy-wise against the conventional centralised shared memory solution in order to reveal which memory allocation is the most appropriate for future mobile architectures. The results show that distributed shared memory allocations bring performance gains and opportunities to reduce energy consumption.Keywords
This publication has 31 references indexed in Scilit:
- Coherence protocol for transparent management of scratchpad memories in shared memory manycore architecturesPublished by Association for Computing Machinery (ACM) ,2015
- Energy-Efficient Cache Design in Emerging Mobile Platforms: The Implications and OptimizationsPublished by EDAA ,2015
- Exploring Efficient Hardware Support for Applications with Irregular Memory Patterns on Multinode Manycore ArchitecturesIEEE Transactions on Parallel and Distributed Systems, 2014
- Evaluation and performance analysis of heterogeneous multicore cluster processor architecturePublished by Institution of Engineering and Technology (IET) ,2014
- Application-aware adaptive cache architecture for power-sensitive mobile processorsACM Transactions on Embedded Computing Systems, 2013
- Scalable Memory Hierarchies for Embedded Manycore SystemsLecture Notes in Computer Science, 2012
- Dark silicon and the end of multicore scalingACM SIGARCH Computer Architecture News, 2011
- The gem5 simulatorACM SIGARCH Computer Architecture News, 2011
- Power-aware microarchitecture: design and modeling challenges for next-generation microprocessorsIEEE Micro, 2000
- The SPLASH-2 programsACM SIGARCH Computer Architecture News, 1995