Novel ECC structure and evaluation method for NAND flash memory
- 1 September 2015
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in 2015 28th IEEE International System-on-Chip Conference (SOCC)
Abstract
The evaluation of error correction code (ECC) for NAND flash memory is increasingly complicated by the increasing bit error rate in memory. The concept of error-free information capacity is proposed to evaluate the performance ECC of NAND flash memory. The new method simultaneously considers the capacity and reliability of NAND flash memory. Low-density parity-check (LDPC) codes with a medium code rate can improve the integrated performance of NAND flash memory in order of magnitudes. Observations provide guides for the development of ECC schemes in NAND flash memory in future. An ECC structure based on adaptive LDPC codes is also presented in this paper. The new structure achieves integrated performance of both capacity and reliability in NAND flash memory.Keywords
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