Bit error rate in NAND Flash memories
Top Cited Papers
- 1 April 2008
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
NAND flash memories have bit errors that are corrected by error-correction codes (ECC). We present raw error data from multi-level-cell devices from four manufacturers, identify the root-cause mechanisms, and estimate the resulting uncorrectable bit error rates (UBER). Write, retention, and read-disturb errors all contribute. Accurately estimating the UBER requires care in characterization to include all write errors, which are highly erratic, and guardbanding for variation in raw bit error rate. NAND UBER values can be much better than 10-15, but UBER is a strong function of program/erase cycling and subsequent retention time, so UBER specifications must be coupled with maximum specifications for these quantities.Keywords
This publication has 17 references indexed in Scilit:
- First evidence for injection statistics accuracy limitations in NAND Flash constant-current Fowler-Nordheim programmingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2007
- Recovery Effects in the Distributed Cycling of Flash MemoriesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- Flash EEPROM Threshold Instabilities due to Charge Trapping During Program/Erase CyclingIEEE Transactions on Device and Materials Reliability, 2004
- Analytical Percolation Model for Predicting Anomalous Charge Loss in Flash MemoriesIEEE Transactions on Electron Devices, 2004
- Erratic erase in flash memories. I. Basic experimental and statistical characterizationIEEE Transactions on Electron Devices, 2003
- Read-disturb degradation mechanism due to electron trapping in the tunnel oxide for low-voltage flash memoriesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Analysis of detrap current due to oxide traps to improve flash memory retentionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A negative V/sub th/ cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memoriesIEEE Journal of Solid-State Circuits, 1999
- Erratic Erase In ETOX/sup TM/ Flash Memory ArrayPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- Novel read disturb failure mechanism induced by FLASH cyclingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993