Register minimization in cost-optimal synthesis of DSP architectures
- 19 November 2002
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
In this paper we propose a generalized technique to count the num- ber of registers supporting overlapped scheduling and a general digit-serial data format. This technique is integrated into an integer linear programming model which minimizes the cost of registers as well as the cost of processors and data format converters to synthesize a cost-optimal architecture for a given digital signal processing algorithm. It is shown that by including the cost of registers in the synthesis task as proposed in this paper leads to upto 12.8% savings in the total cost of the synthesized architecture when compared with synthesis per- formed without including the register cost in the total cost.Keywords
This publication has 14 references indexed in Scilit:
- Synthesis methods for domain-specific multiprocessor systems including memory designPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Synthesis of throughput-optimized multichip architecturesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Loop list scheduler for DSP algorithms under resource constraintsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Zone schedulingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993
- Global optimization approach for architectural synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993
- Optimal synthesis of high-performance architecturesIEEE Journal of Solid-State Circuits, 1992
- A systematic approach for design of digit-serial signal processing architecturesIEEE Transactions on Circuits and Systems, 1991
- Architecture-driven synthesis techniques for VLSI implementation of DSP algorithmsProceedings of the IEEE, 1990
- Force-directed scheduling for the behavioral synthesis of ASICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- Behavioral to structural translation in a bit-serial silicon compilerIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988