Verification of synchronous sequential machines based on symbolic execution
- 1 January 1990
- book chapter
- conference paper
- Published by Springer Science and Business Media LLC in Lecture Notes in Computer Science
- p. 365-373
- https://doi.org/10.1007/3-540-52148-8_30
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- Proving circuit correctness using formal comparison between expected and extracted behaviourPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Design Methodology for Large Custom VLSI ProcessorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1986
- A New Method for Verifying Sequential CircuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1986