A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode

1 January 2006

conference paper
conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 459-466
https://doi.org/10.1109/isscc.2006.1696078

Abstract

A 64Mb chain FeRAM implemented in 0.13mum 3M CMOS technology is described. A quad-BL architecture reduces the die area by 6.5% and realizes 87.5mm ² die with an effective cell-size of 0.7191mum ² while eliminating BL-BL coupling noise. A high-speed ECC circuit and cell data write-back scheme achieves read/write cycle time of 60ns and 200MB/S burst

Keywords

This publication has 3 references indexed in Scilit:

A 0.9-V 1T1C SBT-based embedded nonvolatile FeRAM with a reference voltage scheme and multilayer shielded bit-line structure
IEEE Journal of Solid-State Circuits, 2005
A 32-Mb chain FeRAM with segment/stitch array architecture
IEEE Journal of Solid-State Circuits, 2003
A 76-mm/sup 2/ 8-Mb chain ferroelectric memory
IEEE Journal of Solid-State Circuits, 2001

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