Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product
Top Cited Papers
- 1 May 2020
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The open source RISC-V ISA has been quickly gaining momentum. This paper presents Xuantie-910, an industry leading 64-bit high performance embedded RISC-V processor from Alibaba T-Head division. It is fully based on the RV64GCV instruction set and it features custom extensions to arithmetic operation, bit manipulation, load and store, TLB and cache operations. It also implements the 0.7.1 stable release of RISCV vector extension specification for high efficiency vector processing. Xuantie-910 supports multi-core multi-cluster SMP with cache coherence. Each cluster contains 1 to 4 core(s) capable of booting the Linux operating system. Each single core utilizes the state-of-the-art 12-stage deep pipeline, out-of-order, multi-issue superscalar architecture, achieving a maximum clock frequency of 2.5 GHz in the typical process, voltage and temperature condition in a TSMC 12nm FinFET process technology. Each single core with the vector execution unit costs an area of 0.8 mm 2 , (excluding the L2 cache). The toolchain is enhanced significantly to support the vector extension and custom extensions. Through hardware and toolchain co-optimization, to date Xuantie-910 delivers the highest performance (in terms of IPC, speed, and power efficiency) for a number of industrial control flow and data computing benchmarks, when compared with its predecessors in the RISC-V family. Xuantie-910 FPGA implementation has been deployed in the data centers of Alibaba Cloud, for applicationspecific acceleration (e.g., blockchain transaction). The ASIC deployment at low-cost SoC applications, such as IoT endpoints and edge computing, is planned to facilitate Alibaba’s end-to-end and cloud-to-edge computing infrastructure.Keywords
This publication has 18 references indexed in Scilit:
- A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOIIEEE Journal of Solid-State Circuits, 2017
- A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOIIEEE Journal of Solid-State Circuits, 2016
- SHAKTI Processors: An Open-Source Hardware InitiativePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2016
- Out of order floating point coprocessor for RISC V ISAPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2015
- OpenRISC-based System-on-Chip for digital signal processingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2014
- SIR10US: A tightly coupled elliptic-curve cryptography co-processor for the OpenRISCPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2014
- Analyzing fault effects in the 32-bit OpenRISC 1200 microprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2008
- Niagara: A 32-Way Multithreaded Sparc ProcessorIEEE Micro, 2005
- MIPSACM SIGMICRO Newsletter, 1982
- MIPS: A VLSI Processor ArchitecturePublished by Springer Science and Business Media LLC ,1981