Scheduling tests for VLSI systems under power constraints
- 1 June 1997
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 5 (2), 175-185
- https://doi.org/10.1109/92.585217
Abstract
This paper considers the problem of testing VLSI integrated circuits in minimum time without exceeding their power ratings during test. We use a resource graph formulation for the test problem. The solution requires finding a power-constrained schedule of tests. Two formulations of this problem are given as follows: (1) scheduling equal length tests with power constraints and (2) scheduling unequal length tests with power constraints. Optimum solutions are obtained for both formulations. Algorithms consist of four basic steps. First, a test compatibility graph is constructed from the resource graph. Second, the test compatibility graph is used to identify a complete set of time compatible tests with power dissipation information associated with each test. Third, from the set of compatible tests, lists of power compatible tests are extracted. Finally, a minimum cover table approach is used to find an optimum schedule of power compatible tests.Keywords
This publication has 17 references indexed in Scilit:
- BIST and boundary-scan for board level test: test program pseudocodePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A distributed BIST control scheme for complex VLSI devicesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- PRITI: Estimation of maximal currents and current derivatives in complex CMOS circuits using activities waveformsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A novel approach to cost-effective estimate of power dissipation in CMOS ICsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
- A scheme for overlaying concurrent testing of VLSI circuitsPublished by Association for Computing Machinery (ACM) ,1989
- Test scheduling and control for VLSI built-in self-testIEEE Transactions on Computers, 1988
- Deterministic Processor SchedulingACM Computing Surveys, 1977
- An Efficient Algorithm for Finding an Irredundant Set CoverJournal of the ACM, 1974
- Computer Solutions to Minimum-Cover ProblemsOperations Research, 1969