Prospects for low-power, high-speed MPUs using 1.5 nm direct-tunneling gate oxide MOSFETs

Publisher Website

31 May 1997

journal article
Published by Elsevier BV in Solid-State Electronics

Vol. 41 (5), 707-714
https://doi.org/10.1016/s0038-1101(96)00257-2

Abstract

No abstract available

Keywords

This publication has 4 references indexed in Scilit:

Low-power CMOS digital design
IEEE Journal of Solid-State Circuits, 1992
Incredible shrinking computers
IEEE Spectrum, 1991
Microprocessors circa 2000
IEEE Spectrum, 1989
Performance Limits of CMOS ULSI
IEEE Journal of Solid-State Circuits, 1985

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