On Coding for Endurance Enhancement and Error Control of Phase Change Memories With Write Latency Reduction

Abstract

This paper addresses at coding-level the challenge of providing a write latency reduction with either endurance enhancement and/or error control for a phase change memory (PCM) system. Endurance enhancement is assessed by considering the skewed write operations among the cells of a PCM system, i.e., when the maximal number of cell write operations is smaller, then the coding scheme achieves a better endurance, because the access of the memory cells in the system is more uniform (less skewed). As a first contribution, simulation of different industrial benchmarks shows that for realistic code rates (such as at k/n = 4/5), the write time speed-up (WTS) code not only reduces the write latency as previously reported, but it also reduces the skewed (nonuniform) use of PCM cells. This occurs because the WTS code uses as many cells as possible to reduce the number of SET operations in a PCM cell. Then, error control is considered. An encoding/decoding scheme that is compatible with a write latency reduction code, such as WTS, is proposed. For compatibility with the write latency reduction, a partition-based error control code (ECC) must be used. Also, the ECCs employed in these cases are systematic. The original information always appears in the codeword without modification. Evaluation by simulation shows that also in this case, the maximal number of write operations of the WTS code is smaller.