A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS

Abstract

This paper presents a sub-threshold Field Programmable Gate Array (FPGA) that uses a low-swing dual-V_DD global interconnect fabric to reduce energy and improve delay. A 90nm chip implements the FPGA with 1134 LUTs, which is 2.7X smaller, 14X faster, and 4.7X less energy than a sub-threshold FPGA using conventional interconnect and 22X less energy than an equivalent FPGA at full V_DD.