A parallel 32×32 time-to-digital converter array fabricated in a 130 nm imaging CMOS technology

Abstract

We report on the design and characterization of a 32 times 32 time-to-digital converter (TDC) array implemented in a 130 nm imaging CMOS technology. The 10-bit TDCs exhibit a timing resolution of 119 ps with a timing uniformity across the entire array of less than 2 LSBs. The differential- and integral non-linearity (DNL and INL) were measured at plusmn 0.4 and plusmn1.2 LSBs respectively. The TDC array was fabricated with a pitch of 50 mum in both directions and with a total TDC area of less than 2000 mum ² . The characteristics of the array make it an excellent candidate for in-pixel TDC in time-resolved imagers for applications such as 3-D imaging and fluorescence lifetime imaging microscopy (FLIM).