A 4.4-ns CMOS 54×54-b multiplier using pass-transistor multiplexer

Publisher Website

17 December 2002

conference paper
conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/cicc.1994.379651

Abstract

No abstract available

Keywords

This publication has 3 references indexed in Scilit:

A 1.5 ns 32 b CMOS ALU in double pass-transistor logic
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1993
A 54*54-b regularly structured tree multiplier
IEEE Journal of Solid-State Circuits, 1992
A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology
IEEE Journal of Solid-State Circuits, 1991

Cited by 6 articles