A read-static-noise-margin-free SRAM cell for low-V/sub dd/ and high-speed applications
- 30 August 2005
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 478-611 Vol. 1
- https://doi.org/10.1109/isscc.2005.1494077
Abstract
A read-static-noise-margin-free SRAM cell consists of seven transistors, several of which are low-V, NMOS transistors used to achieve both low-V/sub dd/ and high-speed operation. A 64 kb SRAM macro is fabricated in 90 nm CMOS technology. Both a minimum V/sub dd/ of 440 mV and a 20 ns access time with a 0.5 V supply are obtained.Keywords
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